cdlflatten

cdlflatten reads a hierarchical SPICE/CDL netlist and writes a flat netlist of one cell, with every device given its full hierarchical name. It is used to prepare a hierarchical schematic netlist for transistor-level LVS, and can also be run on its own.

Glade has a built-in copy of this flattener, which it runs when Hierarchical netlist? is checked in Verify->LVS->Run; the dialog's Top Cell Name and Delimiter character fields correspond to the -topcell and -delim options below. The flat netlist can then be compared with an extracted layout by Gemini.

Gemini can itself read a one-level hierarchical CDL netlist, comparing the subcircuit instances as black boxes (see Gemini input netlists). Use cdlflatten when the comparison must be made down to the transistors.

Command line

cdlflatten -topcell cell [-delim c] [-v] -infile in.cdl -outfile out.cdl
cdlflatten -topcell cell [-delim c] [-v] in.cdl out.cdl

Option	Default	Meaning
`-topcell` cell		The `.subckt` to flatten. Required.
`-infile` file		The hierarchical CDL netlist to read. Required.
`-outfile` file		The flat netlist to write. Required; an existing file is overwritten.
`-delim` c	`/`	Delimiter between the levels of hierarchical device and net names.
`-v`		Print the build date and, after reading, the pins, nets and elements of the top cell.
`-h`		Print a summary of the options and exit.

Each option can also be written with two dashes (--topcell, --infile and so on), and the options can be given in any order. Instead of -infile and -outfile, the files can be given as bare names: the first is the input file and the second the output file. cdlflatten exits with status 0 on success. It stops with an error, naming the option, if the top cell or either file is not given, and also if the input file cannot be read or the top cell is not in it.

Input netlist

The input is a CDL file of .subckt ... .ends definitions, read as follows:

Subcircuits. Each .subckt line gives the cell name and its pins; parameter defaults (name=value) after the pins are ignored. *.PININFO lines give pin directions (I, O or B). Lines outside a .subckt are ignored, apart from those below.
Instances. X lines instantiate a subcircuit, written either X1 n1 n2 / cell or X1 n1 n2 cell, optionally followed by name=value parameters.
Devices. MOS transistors (M, four terminals and a model), resistors (R), capacitors (C), inductors (L) and diodes (D) with two terminals, and bipolar transistors (Q) with three. Resistors, capacitors and inductors may have a model name or a value (100 or R=100). Other device types are not read.
Global nets. .GLOBAL and *.GLOBAL lines name nets that are the same at every level of the hierarchy.
Units. *.SCALE METER or *.SCALE MICRON is copied to the output.
Lines starting with + continue the previous line, and other lines starting with * are comments. Names are case-sensitive.

A cell that is instantiated but not defined in the file is reported (Can't find master) and its instances are left out of the output.

Flat netlist

The output is a single .subckt for the top cell, with its pins, *.PININFO, *.SCALE and .GLOBAL lines, followed by every device in the hierarchy:

Device names are the device's own name followed by the path of instances above it, outermost first, so that each name still starts with its device letter. Device MN1 in instance XI2 of instance XB1 becomes MN1/XB1/XI2.
Net names. A net that is connected to a pin of its cell takes the name of the net it connects to in the level above, up to the highest level it reaches. Top-level nets and global nets keep their names. Other nets are named by their instance path, starting with the delimiter: net mid inside XB1 becomes /XB1/mid.
Parameters. A device property whose value is the name of a parameter of the instance directly above it is given that parameter's value. With XI1 a y / inv wp=2u and MP1 ... pch W=wp inside inv, the flat device has W=2u.

For example, this hierarchical netlist:

.GLOBAL VDD VSS
.SUBCKT inv A Y
MP1 Y A VDD VDD pch W=wp L=0.1u
MN1 Y A VSS VSS nch W=1u L=0.1u
.ENDS
.SUBCKT buf IN OUT
XI1 IN mid / inv wp=2u
XI2 mid OUT / inv wp=3u
.ENDS
.SUBCKT top a z
XB1 a z / buf
.ENDS

flattened with cdlflatten -topcell top -infile h.cdl -outfile flat.cdl, gives these devices:

MN1/XB1/XI2  z /XB1/mid VSS VSS nch  W=1u L=0.1u
MP1/XB1/XI2  z /XB1/mid VDD VDD pch  W=3u L=0.1u
MN1/XB1/XI1  /XB1/mid a VSS VSS nch  W=1u L=0.1u
MP1/XB1/XI1  /XB1/mid a VDD VDD pch  W=2u L=0.1u