Change Log 2026

Contents for 2025 can be found here

Version 6.0.20 release on 5/1/2026

- enhancement: Net Browser highlight net cmd uses wider width for nets to make them more easily visible on schematics.

- bugfix: pin obstructions not handled correctly in schematic autorouter.

Version 6.0.21 release on 23/1/2026

- bugfix: fixes to improve schematic autorouter.

- enhancement: Display cursor coords in dbu (as opposed to microns) is now saved to settings file.

- bugfix: Import Calibre error file did not clear existing error markers; now it does.

- bugfix: Net tracer did not always trace through hierarchy.

- bugfix: Drawing hilite of a polygonal shape did not transform the polygon.

- bugfix: Net tracer did not always trace across abutting shapes.

- bugfix: Switching tab windows caused the viewport to be reset to the whole design in Windows; now the viewport is maintained.

- enhancement: Added a selection dialog option to display selected instance contents undimmed when dimming unslected was set.

Version 6.0.22 release on 08/2/2026

- bugfix: Import Skill crashed parsing TSMC28 techfile.

- enhancement: Add layer properties parsing to Skill techfiles.

- enhancement: Better reporting of incorrect labelling (net shapes which have different text labels) during extraction.

Version 6.0.23 release on 19/2/2026

- bugfix: Setting bindkeys to an empty string left them unsettable.

- enhancement: Duplicating bindkeys now gives warning and does not create duplicate.

- bugfix: documentation for ui::importGds2() missed a parameter.

- bugfix: Executing a python script with funcs that referenced other funcs failed with 'undefined function' due to error in global/local dict setting.

Version 6.0.24 release on 05/05/2026

- bugfix: Cadence techfile parser crash reading tsmcN16 techfile.

Version 6.0.25 release on 24/07/2026

- bugfix: minArea read from techfile was getting multiplied by dbu, not dbu*dbu.

Version 6.0.26 release on 09/08/2026

- bugfix: Trace Net cmd allowed labels as seed shapes, and very rarely a text on the same layer as a connect layer would cause a short.

- bugfix: Trace Net cmd speedup by ~20%.

Version 6.0.27 release on 26/09/2026

- bugfix: A fairly significant bug in the tiling algorithm for booleans fixed, which could result in false positives and/or memory corruption.

Version 6.1.0 release on 3/10/2026

- Enhancement: New documentation scheme

Version 6.1.1 release on 13/10/2026

- Bugfix: Wiring devices in schematic would show an incomplete net (shown as a dotted yellow any angle line) when the target was a pin in a device. This was because the obstacle model was not allowing access to the pin.

- Bugfix: Moving instances showed incomplete nets connected to their pins. The problem was similar i.e. the obs map of the moving instance did not have cutouts for its pins.

- Bugfix: Yanks/Paste: the pasted object(s) were not under the cursor, they were insitially shown at the coordinate where the yank was made. Now they are pasted starting at the mouse cursor.

- Bugfix: Using the rotate keys (r/x/y) while in a paste command gave an incorrect paste position.

- Bugfix: Create Pin sometimes showed the moving pin shape to be different from the cursor position.

- Bugfix: DRC area checks (minimum area, area inside a range and hole area) could read past the end of a layer's edges, which could crash with a bus error on large merged layers. Shapes with holes could also overrun the checks' working space.

- Bugfix: Export DEF wrote a pin with several shapes (e.g. VDD, VSS) as several pins with the same name, which is not legal DEF, so Floorplan->Place Cells failed with "DEF parser returns an error" from the placer. The extra shapes are now written as NAME.extra1, NAME.extra2 etc., as Import DEF expects. Reading the placement back also kept only the last shape of such pins; now it keeps them all.

- Enhancement: Global router (Floorplan->Route->Global Route). The design is divided into gcells; each net gets a Steiner tree, split into two-pin segments that are pattern routed shortest first. Segments crossing overflowed gcell edges are then ripped up and rerouted with a maze router, with history costs and a growing overflow penalty, until there is no overflow or it stops improving, and a layer is assigned to each part of each segment. The result is shown as a congestion map, and Display Globally Routed Net shows a net's route. Scripted with ui().globalRoute().

- Enhancement: Detail router (Floorplan->Route->Detail Route). Each net is routed with a multi-layer A* search on the layers' tracks, inside the gcells of its global route, and the wires and vias are written into the design. Multi-pin nets are grown as trees from pin access points worked out for each cell. Failed connections are retried in a larger area, then rip-up and reroute and pin-clearing passes route the nets still failing. Routing keeps the layer spacing, avoids end of line violations and patches pieces under the minimum area, using other via orientations where the default via would break a rule; optionally it keeps the wider spacing of spacing tables and runs design rule repair passes. Settings are in Detail Route Options. Scripted with ui().detailRoute().

- Enhancement: LEF import reads more of the technology into the techfile: each routing layer's PITCH (including PITCH x y), OFFSET, AREA, end of line spacing (SPACING ... ENDOFLINE ... WITHIN) and parallel run length spacing table (SPACINGTABLE PARALLELRUNLENGTH), and the MANUFACTURINGGRID. The techfile has new MINEOLSPACE and MINSPACETABLE rules to hold them.

- Bugfix: libgeom had a memory corruption issue when resizing working space. This could result in errors like "Can't find neighbour edge for vert edge...""

- Enhancement: KDtree made thread safe and re-entrant for router.

- Enhancement: Gemini (netlist comparison) now reads DEF files as well as CDL files, so it can compare DEF against DEF or DEF against CDL. It reads the DEF's connectivity (COMPONENTS, PINS, NETS and SPECIALNETS, including ( * pin ) wildcards) and one level of hierarchical CDL (the top .subckt and its X instances), with cells compared as black boxes. New options: -k keeps physical-only instances, -V names supply nets, -W ignores supply pins, -T sets the top cell.

- Enhancement: Detail router is now multithreaded. Nets (and design rule clips) whose areas don't meet are routed at once, and the result is the same on any number of threads. The first pass, minimum area patches, design rule clip passes and the final check use the threads; on 16 threads the ISPD-18 test2 design routes about 3x faster. The number of threads is set in Detail Route Options (default: the CPU's cores on ARM, twice its cores on x64; 0 routes one net at a time). The options dialog is now on two tabs and adds the region and clip pass settings.

- Bugfix: DEF export wrote some stacked vias in an order DEF readers can't follow, e.g. a Metal2 wire then VIA12 VIA23 in the same statement (after VIA12 the route is on Metal1, where VIA23 can't start). Reading such a DEF back put wires on the wrong layer (shorts and opens). Each via now continues a statement only from the layer the statement is on; otherwise it starts a NEW statement.

- Enhancement: Detail Route Options has a Fast flow (experimental) option for large designs: connections are routed on the threads as soon as none nearby is being routed, failed connections are retried crossing other nets at a cost, clashes are repaired in negotiating design rule clips, cuts get a via turned a quarter (_FR, written to the DEF's VIAS) where the default via's pad lies across the tracks, and searches and repair have time limits. ISPD-18 test4 routes in about 5 minutes on 16 threads with no opens or shorts.

- Enhancement: Global Route Options has Target layers by run length, which steers each run to a layer by its length and saves vias; the fast flow turns it on.

- Enhancement: Detail Route Options has Mark unrouted pins, which puts a marker (rule "Route: unrouted pin") on each unconnected pin of the failed nets at the end of routing, for the DRC marker browser. The route now reports its total time, global and detail, and logs its setup steps as they start.

- Bugfix: Cancel in the detail route's progress dialog could hang or crash while threads were routing. It now stops within a few seconds, keeps the routing finished so far and counts the unfinished nets as failed.

- Enhancement: Much faster merging of layers in the geometry engine, used by DRC, extraction and boolean operations, especially for dense or arrayed layouts. Adding an edge to the scanline no longer looks at every edge above it, stacks of identical overlapping edges are counted once rather than repeatedly, and repeated copies of the same shape (e.g. from overlapping array cells) are dropped before merging. The merged result is unchanged. Reading the layers of a 256 word SRAM for extraction went from about 340s to 6s.

- Enhancement: Faster device extraction. Each distinct device geometry now builds its device PCell once per run and identical devices share it, instead of the PCell being reloaded and rebuilt for every device. Extracting the MOS devices of a 256 word SRAM went from about 25s to 2s per device type.

- Enhancement: Much faster DRC checks on dense layouts. Each edge is now compared only with nearby edges rather than with every other edge on the scanline, and looking up the shape an edge belongs to no longer searches the whole layer. DRC violations are unchanged. On a 256 word SRAM: spacing checks are up to about 60x faster (metal1 spacing 35s to 0.6s), enclosure checks up to 25x, overlap checks about 17x and width checks about 3-6x. Extension checks, which on large layers could run for many minutes, now take under a second. Notch, line end, multiple and 2D spacing, length spacing and boolean enclosure checks get the same improvement.

Version 6.1.2 release on 20/10/2026

- Bugfix: Gui could crash on exit if there were redraw ops running in the thread during exit.

- Enhancement: Much faster net tracing (Verify > Trace Net, ui.traceNet and ui.traceLabel). Each traced shape's neighbours are now searched for once per layer rather than once per trapezoid per connect rule, shapes already traced are skipped before being broken into trapezoids, and each shape is broken into trapezoids only once. The search no longer leaks memory. Tracing a 430,000 shape net of a 256 word SRAM takes about 110s; it previously ran for over 10 minutes using 27GB of memory without finishing.

- Bugfix: The net tracer treated different shapes with the same bounding box and layer as one shape, so it could miss the shapes connected to the others.

- Bugfix: Saving traced shapes to a cellView put shapes from instances at their master cell's coordinates rather than where they are placed, and was very slow for large nets (the layer's search tree was rebuilt for every shape saved). Saving the SRAM power net now takes under a second.

- Bugfix: A techfile CONNECT rule written as CONNECT lyr1 TO lyr2 BY via (rather than CONNECT lyr1 BY via TO lyr2) had its via layer ignored, so the net tracer connected the two layers wherever they overlapped. Both orders are now read, and a CONNECT rule with an unknown token or a missing layer is reported rather than added. In the FreePDK45 techfile this joined every metal layer to the next: the SRAM power net above traced 430,000 shapes, most of the design, and now traces 2,694.

- Enhancement: The net tracer can find shorts. Given two points (or two labels) that should be on different nets, it traces from both at once and finds the shortest chain of shapes connecting them, which it highlights, with the shape where the two traces met in a second colour, and lists in the log. Use the Point 1 and Point 2 buttons, or Short trace from label1 to label2, in Verify > Trace Net, or ui.findShort and ui.findShortLabels from Python.

- Bugfix: ui.traceNet and ui.traceLabel always highlighted in yellow, ignoring their colour arguments, and assigned the traced shapes to the named net even when addConnectivity (useLabelNameForNet for traceLabel) was False. Both now do as documented.

- Bugfix: The net tracer missed a via connection when the via was as wide as the shape it lands on (the overlap test found no overlap when the two shared their left and right edges), and counted shapes that only abut as overlapping. The trapezoid overlap and touch tests are now exact. On the SRAM above this joins the vdd straps to the rest of the vdd net (293,034 shapes) that the CONNECT fix left apart.

- Enhancement: Faster net tracing of long, thin shapes such as power straps: the shapes found around each traced shape are indexed by a grid that follows its shape. Tracing the SRAM vdd net takes 84s, or about 0.3ms a shape, down from about 14ms a shape.

- Enhancement: The net tracer no longer traces again from a shape identical to one it has already traced from (the same rectangle, segment or via in overlapping cells, which in the SRAM is most of them); the copies are still part of the traced net. It also adds every via on a traced shape rather than just the first. The SRAM vdd net now traces in 19s (search results are also kept in reused buffers rather than lists).

- Bugfix: Two edges were taken as colinear when one contained just the first point of the other, rather than both of its points (used by the net tracer and in MOS and MIM cap extraction).

- Bugfix: Merging a layer could give a hole to the wrong polygon: when finding the polygon around a hole, a boundary that turned through a vertical edge on the scanline was not followed, so the hole was given to a polygon further out. Extraction then connected a via touching the hole's edges to that polygon's net. In the 256 word SRAM this joined vdd to gnd, which LVS reported as a short although the layout has none.

- Enhancement: The text editor (File->Edit Python file..., renamed from Edit Ascii File...) has a Python debugger for scripts and PCells, used like Visual Studio's: Start/Continue (F5), Step Over (F10), Step Into (F11), Step Out (Shift+F11), Stop (Shift+F5), and breakpoints set by clicking left of a line number (F9). When stopped it shows the call stack, the local variables of the selected frame and an evaluate panel, and an unhandled exception stops where it was raised. A PCell is run into a cellView chosen with its argument values, shown in a layout window that is redrawn at every stop. The editor is no longer modal. See Python Debugger.

- Bugfix: Glade could hang at 'Optimising...' after importing a layout (e.g. OASIS) with several large layers. Each large layer's search tree is built on its own thread, and building a tree started further threads from the same pool; once every thread was building a tree, those further threads never ran, so the builds waited for ever. A tree build now does the work itself when no thread is free.

- Enhancement: Exporting OASIS with repetition compression is faster: a design with 7.8M instances and 4.3M paths in its top cell now exports in 12s rather than 18s. Identical paths and polygons are now found and written as repetitions, so files can be a little smaller.

- Enhancement: Exporting OASIS or GDS2 shows a progress bar in the status bar, as importing does.

- Bugfix: Exporting OASIS with instance compression dropped instances of cells that were not found, and two different cells, or two different text strings, could rarely be written as one repetition.