In version 4.4.70 the first version of netlist driven layout has been implemented. The idea is that given a SPICE/CDL netlist (e.g. used for simulation), layout can be created with the correctly sized PCells and connectivity info.
The flow requires PCells for each device in the netlist e.g. MOS P/N devices, resistors, capacitors etc. The PCells need pin shapes e.g. poly/diffusion pins for S/G/D/B nodes. Examples can be found in the distribution.
The Tools->Netlist View menu opens a text window, and from this you can open a netlist. The netlist is shown in this window, with syntax highlighting. It can be edited here if required, saved etc. But also you can use the 'Gen Layout' menu item to create a layout cellView containing the instances from the netlist and their connectivity. Instances are placed purely in clusters according to device type; they can then be manually moved. With the Selction Options 'Show Connectivity' option enabled, flightlines are shown between device pins.
Cross-probing and cross-selection between the netlist and layout is possible, either for instances, nets or devices. M factor MOS devices are supported (again the distribution contains an example netlist featuring devices with w/l/m parameters).
Manual routing has been enhanced so that with the cursor over an instance pin, the starting/ending point is snapped to the pin centre and takes the layer of the pin, and the net the pin is connected to.
Various other capabilities will be added in future, as will documentation on using this flow.