Version 4.0.26 is in the works at the moment as I have some spare time :xd:
Some fixes to the pcell code and pcell instanciation, plus (not yet checked in) MOS device extraction. Hopefully the ability to extract and export a SPICE netlist of simple cells.
The extraction is actually up and running, and will recognise 3 terminal MOS devices currently (4 terminal should be a pretty easy extension). Also device L and W can be determined for transistors with straight or bent gates.
Update: the extractMOS command is now working after a bit of coding to get the device width/length working for gates with all angle bends. The geomLabel command now labels shapes according to text names and creates top level pins in the extracted view. And an Export CDL command lets you write a flat CDL netlist of an extracted view (I haven't even started thinking about hierarchical extraction / netlisting yet…)
To do is a general purpose device extraction command suitable for diodes/resistors/capacitors/bipolars etc. This in itself is easy, the work is providing the capability to extract parameter info for devices which means a lot more geometry code in the scanline algorithm.
Also in this version there are some bugfixes for edit in place and some changes for the stretch command – this now keeps 45 degree edges at 45 degrees, and stretching adjacent manhattan edges will keep a 45 degree edge if 'Lock diagonals' is checked in the stretch options dialog, which is the default.