[Keith]

Did it work?

[Keith]

Try again now…

[Keith]

Hi Jofre,

I suspect either the upload of the 32 bit version went wrong or the version you have is still the old one, perhaps cached. I have uploaded both 32 and 64 bit versions again.

Try running 'strace' to see where it is looking for the plugins:

strace glade &> tracefile

For me it seems to find them in the right place:

Code:

lstat64("/home", {st_mode=S_IFDIR|0755, st_size=4096, …}) = 0
lstat64("/home/keith", {st_mode=S_IFDIR|0755, st_size=4096, …}) = 0
lstat64("/home/keith/glade4_linux32_ub10", {st_mode=S_IFDIR|0755, st_size=4096, …}) = 0
lstat64("/home/keith/glade4_linux32_ub10/bin", {st_mode=S_IFDIR|0755, st_size=4096, …}) = 0
lstat64("/home/keith/glade4_linux32_ub10/bin/platforms", {st_mode=S_IFDIR|0755, st_size=4096, …}) = 0
lstat64("/home/keith/glade4_linux32_ub10/bin/platforms/libqlinuxfb.so", {st_mode=S_IFREG|0755, st_size=197195, …}) = 0
open("/home/keith/glade4_linux32_ub10/bin/platforms/libqlinuxfb.so", O_RDONLY|O_LARGEFILE|O_CLOEXEC) = 4

i.e. in the $GLADE_HOME/bin/platforms directory.

regards

Keith

[Keith]

Hi Francesc,

Are you saying it works in 4.3.58 but not in 4.4.0?

I'm not clear how to reproduce this.

regards

Keith

[Keith]

Hi Jofre,

The Qt5 port apparently requires some different distribution libs. I have updated them (hopefully) and am uploading them to the website. Please check the 32 and 64 it versions; if OK, let me know.

regards

Keith

[Keith]

For anyone who downloaded Glade 4.4.0 before today, please re-download it, as there some missing DLLs/shared libs due to Qt5 being 'modularised'.

[Keith]

Glade 4.4.0 is shortly to be released, which makes a move from Qt 4.8.x to Qt 5.1.1. Although the porting has not been as bad as the Qt3 to 4 fiasco, there are still several issues that have caused problems and although the regression testing has picked up some of these, others are more cosmetic and/or tricky.

So when it's released (Win32/64 platforms will come first as they still represent two thirds of the downloads) please back up the current 4.3.58 that I hope you are using (if not download it now!) and try out carefully.

Win32/64 platforms are up now and Ubuntu 64 bit is just uploading. It's a slow process for the Linux versions as the VM's have to be updated to support xcb which is now required for Qt 5.x, and the new version of Qt compiled etc etc…

[Keith]

Hi Francesc,

That's good to hear. The other platforms are uploading; I will update the index page when they are all there. Have a good weekend!

regards

Keith

[Keith]

Hi Francesc,

I have fixed the TFT extraction algorithm. Basically now it expects the recognition region, the gate layer and the S/D layer.

For each device identified by the recognition region, it measures the sum of the lengths of the S/D layer edges that abut or overlap the recognition region.

It then calculates the width of the device as the total edge length divided by the number of edges (warns if not exactly 2), and the length of the device as the area of the recognition region divided by the width.

It appears to give correct answers for all the testcases I have from you. I'll re-build 4.3.58 (there is also a couple o fminor other fixes I want to do) then update it for all platforms.

regards

Keith

btw the extraction rule for the last example now looks like:

Code:

# Initialize boolean package
from ui import *
ui = cvar.uiptr
cv = ui.getEditCellView()
geomBegin(cv)
lib = cv.lib()

ui.loadPCell(lib.libName(), "ofet")

cond1 = geomGetShapes('Cond1', 'drawing')
cond2 = geomGetShapes('Cond2', 'drawing')
via = geomGetShapes('VIA', 'drawing')
OSC = geomGetShapes('OSC', 'drawing')
idTRT = geomGetShapes('idTRT', 'drawing')

# Gate recognition region
gate_region = geomAndNot(geomAnd(cond1, idTRT), cond2)

geomLabel(cond1, "Cond1", "pin")
geomLabel(cond2, "Cond2", "pin")

geomConnect([
[ via, cond1, cond2 ],
])

saveInterconnect([ via,
cond1,
cond2
])

extractTFT('ofet', gate_region, cond1, cond2)

# Exit boolean package, freeing memory
geomEnd()

# Open the extracted view
ui.openCellView(lib.libName(), cv.cellName(), "extracted")
cv_ex = lib.dbFindCellViewByName(cv.cellName(), "extracted")

[Keith]

Hi Francesc,

This may take a bit of time to get right. It is not as simple as a MOS device extraction where the gate intersects the S/D. Here the gate overlaps multiple S/D shapes.

I'm away the next couple of days so stay tuned…

regards

Keith

[Keith]

I get:
The requested URL /~fvila2/extraction_test_case.zip). was not found on this server.

wait – stripping off the ). got it to work…

[Keith]

Hi Francesc,

I have fixed the microns issue and uploaded new win32/64 binaries.

If you have an example that gives incorrect results still, I'd like to see it.

regards

Keith

[Keith]

Hi Francesc,

I have put a build of 4.3.57 for win32/64 on the website. It has a fix for this problem; I'm not entirely happy with it so I'd appreciate it if you could test it if possible before I run the builds on other platforms.

I had to make a few changes to your extract script:

Code:

# CSEM netlist extraction

# Initialize boolean package
from ui import *
ui = cvar.uiptr
cv = ui.getEditCellView()
geomBegin(cv)
lib = cv.lib()

print "n# Loading extraction PCells"

ui.loadPCell(lib.libName(), "ofet")

print "# Get raw layers"
cond1 = geomGetShapes('Cond1', 'drawing')
cond2 = geomGetShapes('Cond2', 'drawing')
via = geomGetShapes('VIA', 'drawing')
# OSC = geomGetShapes('OSC', 'drawing')
idTRT = geomGetShapes('idTRT', 'drawing')

print "# Form derived layers"
print "# 1. OTFTs"

# Gate region is cond1 AND device gate area
gate_region = geomAndNot(geomAnd(cond1, idTRT), cond2)
# New cond1 layer is everything outside gate_region
cond1_layer = geomAndNot(cond1, gate_region)
# New cond2 layer is everything outside gate_region
cond2_layer = geomAndNot(cond2, gate_region)

print "# Label nodes"

# if geomNumShapes(cond1pin) > 0:
print "# Labeling Cond1…"
geomLabel(cond1_layer, "Cond1", "pin")

# if geomNumShapes(cond2pin) > 0:
print "# Labeling Cond2…"
geomLabel(cond2_layer, "Cond2", "pin")

print "# Form connectivity"

geomConnect([
[ via, cond1_layer, cond2_layer ],
])

print "# Save interconnect"

saveInterconnect([ via,
[cond1_layer, "Cond1"],
[cond2_layer, "Cond2"]
])

print "# Device extraction"
print "# 1. Extract OTFT devices"

extractTFT('ofet', gate_region, cond1_layer, cond2_layer)

# Exit boolean package, freeing memory
print "# Extraction completed."
geomEnd()

# Open the extracted view
ui.openCellView(lib.libName(), cv.cellName(), "extracted")

ALso the techfile layers were not compatible with the GDS2, here is what I belive are the correct mappings:

Code:

LAYER Cond1 drawing 100 10 (0,0,255,255) t t backslash5 solid ;
#LAYER Cond1 pin 101 20 (0,0,255,255) t t solid solid ;
LAYER VIA drawing 90 30 (255,0,0,255) t t cross thick ;
LAYER OSC drawing 80 10 (165,165,165,255) t t dots_rare solid ;
LAYER Cond2 drawing 70 10 (0,255,0,255) t t slash7 solid ;
LAYER Cond2 pin 101 20 (0,255,0,255) t t solid solid ;
LAYER Diel1 drawing 60 20 (255,255,0,255) t t dots_rare2 solid ;
LAYER NoDRC drawing 10 60 (0,255,255,255) t t empty solid ;
LAYER idTRT drawing 11 60 (255,128,0,255) f f empty solid ;
LAYER idDIO drawing 12 60 (255,128,0,255) f f empty solid ;
LAYER idRES drawing 13 60 (255,128,0,255) f f empty solid ;
LAYER idCAP drawing 14 60 (255,128,0,255) f f empty solid ;
LAYER idIND drawing 15 60 (255,128,0,255) f f empty solid ;
LAYER text drawing 0 0 (255,255,255,255) t t empty solid ;

Lastly in the ofet.py extraction pcell I removed the w/l arguments as these are not required – only the cv and ptlist are needed.

regards

Keith

[Keith]

Hi Francesc,

unfortunately what I suggested to you doesn't work properly as the connectivity extraction is incorrect. I did manage to fix the double counting of device widths, though.

The problem with this particular layout style is, as I said, different from the previous one. It might take a few days to figure out a good solution that is applicable to both TFT styles.

I can *almost* get it to work by removing the gate recognition region from cond1/cond2. This means that the S/D correctly abuts the gate, and the gate metal (cond1) also abuts the gate. However the width is calculated slightly wrong as if considers the abutment of all 4 gate edges – i.e. it gets (w+l) instead of just w. There should be a way to fix this though… watch this space.

regards

Keith

[Keith]

Hi Francesc,

Some preliminary findings:

1) your techfile gds property numbers don't match the GDS – I have edited them to what I think they should be, but you are the best person to check…

2) The TFT extraction code was based on an earlier example, this one seems different. The main problem is that the extractTFT() operation is being called with a gate layer that overlaps the S/D layer. To get the device W/L a function is called that expects the S/D polygons to be coincident with the gate layer. This can probably be improved but in the meantime the workaround is to change the extract rules to make the device look like a more normal FET.

To fix that I have added in the extraction rules the following derived layers:

gate_layer = geomAndNot(cond1, cond2)
sd_layer = geomAndNot(cond2, gate_layer)

then for connectivity:

print "# Form connectivity"

geomConnect([
[via, gate_layer, sd_layer],
])

print "# Save interconnect"

saveInterconnect([
[gate_layer, "Cond1"],
[sd_layer, "Cond2"],
via
])

Lastly for the extraction command itself,

extractTFT('ofet', ofet_recognition, gate_layer, sd_layer)

This *almost* works, however the device widths are being calculated as 2x too large… I am checking why this is…

regards

Keith

[Author]

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