[Keith]

I'll take a look. That function was written for the schematic extractor. Why are you trying to merge nets?

[Keith]

Cadence has a display.drf file that merely sets up the colors, line styles and fill patterns for layers – the 'packet' definitions. You have to remember that this was set up in the early 80's and designed for X11, and is not really the way things should be done today. It's ancient code.

The library tech file has the mapping between layers and the packets. It's the latter which is the most important. It can be written but is not normally shipped with the PDK. It contains the mapping of layers to packets and also stuff like GDS mapping, via definitions, MPPs etc.

[Keith]

Would need to see code example to comment. You are going into code areas that are not really supported outside the internal database – what are you trying to do?

cdb::cellView::dbMergeNet(cdb::net *&from, cdb::net *to)

[Keith]

I'll take a look. Currently these are implemented using SWIG %extend functions e.g.

/* helper function to get a list of nets from a cellView */
%extend cdb::cellView {
PyObject * getNets() {
static PyObject *result = NULL;
NetHashTable *nets = self->getNetHashTable();
if (nets) {
result = PyList_New(0);
for (NetHashTable::Iterator iter = nets->begin(); iter; ++iter) {
cdb::net *obj = (cdb::net *) iter.GetValue();
PyList_Append(result, (PyObject *) SWIG_NewPointerObj(obj, SWIGTYPE_p_cdb__net, 0));
}
}
return result;
}
}

[Keith]

In Cadence libInit.il is normally used to set up PCells for a library. I very much doubt it will have all the tech info that Glade needs.

You need to go into Cadence, in the CIW go to Tools->Technology File Manager then click on 'Dump' and pick your technology PDK lib name.

[Keith]

I assume what you are asking is how to import technology info to Glade from a Cadence environment.

You need to use the File->Import Cadence Techfile command. It needs:

1. A Cadence display resources file (usually called display.drf)
2. A Skill tech file dumped from the Cadence tech lib
3. Optionally a GDS layer map file with layer name/purpose and GDS layer number/datatypes mappings.

[Keith]

Sorry for not noticing this earlier. It depends on how you created your inverter schematics – looks like you have the vdd and gnd nets as local, not global nets. Did you use the symbols for vdd/gnd that contain global nets e.g. vdd! / gnd! ?

[Keith]

Are the geometries on the top side actually off grid? Check the instance origin and that the pcell shapes are on grid e.g by querying them.
If they are on grid I?ll take a look, but am on vacation till next Friday so won?t get round to it until then.

[Keith]

Hi Paco,

Sorry about that. There was an issue with that patch, I have rebuilt it and it's on the server now (compile date 8th Nov).

You'll notice that now when you save a library, the DB will be version 550.

regards

Keith

[Keith]

Hi Paco,

It appears the library glade.lib file is corrupted.

It's hard to tell exactly what went wrong… Basically your MPP rules have become corrupted. You might be able to recover by:

– create a new, empty library with the techfile.
– copy the glade.lib from this library into the bad lib

regards

Keith

[Keith]

So there were a couple of bugs causing this issue. The first was that any view containing the string 'spice' was being set as a symbol view. This is actually no longer necessary as in library version 540 and above, viewTypes of views are saved to the library.

The second was more subtle, the reading of the viewTypes was incorrect if MPPs were present in the library (which explained why it worked on my testcase).

Lastly there was another bug that could cause a crash when copying cellViews containing instances, this has also been fixed.

Rather than release a new version, v4.6.64 has been patched with these fixes, and uploaded to the server.

[Keith]

Hi Paco,

Can you give me a small example – not sure if the other one can be used perhaps? It's possible there is some other problem that my tests have not shown.

Thanks,

Keith

[Keith]

4.6.64 is available now on the server.

[Keith]

Ok I have fixed the issue. It will be in v 4.6.64.

I've also cleaned up the netlisting of parasitics; previously capacitors with the pin names swapped were reported as two separate capacitors, now they are merged into one. Also capacitors with the same net names (i.e. shorted) are filtered out.

[Keith]

Thanks Paco I will take a look. I have an idea what might be causing it, just need to test the theory out.

regards

Keith

[Author]

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