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Hi Keith,
I came across a bug where I'm getting minimum area error if I create a closed path.
Ex: Active min area is 0.205um
When I create a closed path of active with width 1um the error seems to flag. This happens only when I create a ring like structure (something like isoaltion rings)Sorry, we were unable to update the post for the attachments. The topic/post was however entered properly and the attachments were also saved. If you wish to go to the topic please click here.
This is the exact message I'm getting when I attach image.
Regards,
RiyazAs you can see the image attached,
Both of the cases i.e. parallel and perpendicular space is less than 0.60um but error flags only for perpendicular. My expectation was that error should not have flagged to either as the paths width is less than 10um for all the geometriesRegards,
RiyazI wanted to know how exactly the spacing check w.r.t width criteria works,
Because I see the rule considering reference as edge and then checks spacing with another line which is perpendicular to it.
Ex: A line end of MET1 is perpendicular to a MET1 PATH which is <10um long but having width less than 10um say some 1um. So why does DRC error still flag here.
I will attach a reference image for your convenience tomorrow.
Regards,
RiyazHi Keith,
I was using the above command for the following rule
"min. space between M1 lines with one or both M1 line width are greater than 10um must be 0.60um"But the issue here is its taking the length also into consideration. I took 2 paths each of 0.25um width and 11um length, when i keep them in parallel way i dont get any error, but if I keep them perpendicular I get the above error, Basically its seeing that if one of the edge is longer than 10um not specifically its length. So please let me know how to go about this.
Regards,
RiyazThank You Keith,
One more query I have is about the series and parallel resistors.
If I have series resistors, do they get reduced to one equivalent resistor when Gemini reduces them (Just like transistors), Also the same for parallel case.
Regards,
RiyazHi Keith,
I constructed a schematic and also an equivalent layout of it, Gemini gives me net mismatch for intermediate nodes/nets which doesn't have any label names(The net names it takes for them in schematic is different when compared to the net names it takes in layout), In analog circuits we do get many such cases where the connects will be intermediate but Gemini reports them as nets mismatch.
Is there any way or option that could help me fix this.
Regards,
RiyazYes I want to create a path with start and end vertices being same. Actually I wanted to create a ISO Ring so I thought to take help on this.
Hi Keith,
I wanted to create a closed path.. or maybe a polygon with hole.
Any help on this would be really appreciated.
How should I choose the x and y points for the array. I did read the posts above, but getting a bit confused on creating a closed path.Regards,
RiyazHi Keith,
I tried to install glade on Windows 7 64bit machine but I'm getting the following error.
Initially it asked for some missing dll files which we added to relevant system folders after which its giving us the error as
"The application was unable to start correctly(0xc000007b). Click OK to close the application"Thanks,
RiyazHi Keith,
As I was going through the change-log, I noticed the below enhancement.
Can you elaborate on this?
My understanding was, that just like example.tch file allows me to create via from create via option, Does this is now applicable for all the cadence techifles too?
viaLayers(
;( layer1 viaLayer layer2 )
;(
)
( POLY CONT MET1 )
( MET1 VIA1 MET2 )
( MET2 VIA2 MET3 )
( MET3 VIA3 MET4 )
( MET4 VIA4 MET5 )
( MET5 VIA5 MET6 )
) ;viaLayers
Are the via layers, does this directly allows me to create via instances without the need of any special coding etc?– enhancement: Import Cadence techfile no reads std. via definitions.
